The present invention relates to a mask for manufacturing a semiconductor device, and a method of forming a semiconductor device using the same.
As semiconductor devices become more highly integrated, the size of semiconductor devices decreases. In particular, in the case of a flash memory, many more devices have to be integrated on a semiconductor substrate to increase the storage capacity of memory. Accordingly, the density of semiconductor devices has increased, and the configuration of the circuit has become more complex.
FIG. 1 is a plane view showing a conventional semiconductor device including drain contacts 40 of a flash memory 10.
The drain contacts 40 are very densely arranged between a first gate 20 that is a drain selection line and a second gate 30 that is a source selection line corresponding to the drain selection line at an edge of a mat region 15.
FIG. 2 is an enlarged view of a drain contact portion {circle around (a)} of FIG. 1.
As semiconductor devices have become more highly integrated, the gap ‘D’ and the pitch ‘P’ between adjacent drain contacts 40 has decreased. Thus, the possibility that a bridge error may occur between the drain contacts 40 has increased. Furthermore, the distance ‘G’ between the drain contact 40 and each gate 20, 30 is larger than the gap ‘D’ between the drain contacts 40.
FIG. 3 is a drawing showing a conventional semiconductor device in which the drain contact formation process is completed.
Referring to FIG. 3, the size {circle around (y)} of the drain contact and the gap {circle around (x)} between the drain contacts are decreased in a highly integrated device. Thus, the possibility that a bridge error may occur is highest at the region where the distance between adjacent drain contacts is the smallest (i.e., the center region).
FIG. 4 is a drawing showing a conventional pattern which is formed in a lithography mask.
Referring to FIG. 4, a pattern 60 defining a drain contact region on a mask 50 is linearly arranged. When the patterns 60 are arranged linearly, like the simulation result of FIG. 3, the gap between the drain contacts which is formed by the pattern 60 becomes narrower, thereby increasing the likelihood of a bridge error.
FIG. 5 is a drawing showing the region in which the intensity of radiation of incident light is concentrated in the lithography process. FIG. 6 is a drawing showing the result of a simulation.
When the exposure energy passes through the mask 50, the intensity of radiation is concentrated on a central area 70 of the pattern 60 defining the drain contact region.
Accordingly, if the regions in which the intensity of radiation is most concentrated are adjacent to each other, the interval between the central areas may also be exposed to light due to the mutual operation of the incident light. In this case, the drain contact can be bridged between the central areas in a subsequent process.
FIGS. 7a to 7e are drawings showing the formation of a drain contact according to DOF (Depth of Focus).
FIG. 7a shows the formation of a drain contact which is normally formed in a best focus. FIG. 7b shows the drain contact when a + defocus is generated. FIG. 7c shows the drain contact when a ++ defocus is generated. FIG. 7d shows the drain contact when a +++ defocus is generated.
In case of a +++ defocus is generated while the drain contact is arranged linearly, the size of the drain contact rapidly decreases.
Furthermore, FIG. 7e shows that a ++++ defocus is generated. In this case, the drain contact is not formed.
That is, when the drain contact pattern is arranged linearly, the process margin is reduced.